The business of producing dynamic random access memory (DRAM) devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance are the key factors that determine the economic success of such a venture.
Each cell within a DRAM device, an individually-addressable location for storing a single bit of digital data, is comprised of two main components: a field-effect access transistor and a capacitor. Each new generation of DRAM devices generally has an integration level that is four times that of the generation which it replaced. Such a quadrupling of device number per chip is always accompanied by a decrease in device geometries, and often by a decrease in operating voltages. As device geometries and operating voltages are decreased, the DRAM designer is faced with the difficult task of maintaining cell capacitance at an acceptable level. This must be accomplished without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process. All DRAM memories of 4-megabit and greater density utilize cell designs having three-dimensional capacitors. Although both trench and stacked capacitor designs have proven serviceable at the 4-megabit level, most manufacturers now seem to favor the stacked capacitor design for its manufacturability and somewhat higher yield. Cup-shaped capacitors which are formed in a cavity made in a sacrificial mold layer are proving to be very popular stack designs for 16-megabit and 64-megabit devices.
A problem associated with the formation of cup-shaped capacitors involves the singulation process whereby individual storage-node plates, which were formed from a single continuous layer of conductive material (generally doped polycrystalline silicon or doped amorphous silicon), are separated from one another. Singulation may be accomplished using a chemical mechanical polishing (CMP) step which removes only the uppermost horizontal expanses of the continuous layer. Although CMP is effective, it is a relatively complex and costly step.
Singulation may also be accomplished with a simple, inexpensive plasma etch-back step which removes all unprotected horizontal expanses of the continuous layer. By applying a photoresist layer prior to the etch-back step, the floor of the cup-shaped storage-node plate can be protected from the etch. In any case, ion bombardment during the plasma etch-back step typically results in a facet etch of the upper edge of the cup-shaped storage-node plate. This sharpening of the upper edge has two problems associated therewith. First, the sharpened edges tend to break off and cause particulate failures. Second,the sharpened edge results in a higher electric field, which can cause charge leakage between the storage-node plates and the cell plate (i.e., the other capacitor plate).
What is needed is a manufacturing process for cup-shaped capacitors which will eliminate the problem of sharpened upper edges of the storage-node plates.